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this is information on a product in full production. january 2013 doc id 023977 rev 1 1/13 13 STL8N10LF3 n-channel 100 v, 25 m typ., 7.8 a stripfet? iii power mosfet in a powerflat? 5x6 package datasheet ? production data features logic level v gs(th) 175 c maximum junction temperature 100% avalanche rated applications switching applications automotive description this device is an n-channel enhancement mode power mosfet produced using stmicroelectronics? stripfet? iii technology, which is specifically designed to minimize on- resistance and gate charge to provide superior switching performance. figure 1. internal schematic diagram order code v ds r ds(on) max i d STL8N10LF3 100 v 35 m 7.8 a (1) 1. the value is rated according to r thj-pcb powerflat? 5x6 1 2 3 4 !-v $ ' 3 table 1. device summary order code marking package packaging STL8N10LF3 8n10lf3 powerflat? 5x6 tape and reel www.st.com
contents STL8N10LF3 2/13 doc id 023977 rev 1 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STL8N10LF3 electrical ratings doc id 023977 rev 1 3/13 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 100 v v gs gate-source voltage 20 v i d (1),(2) 1. specified by design. not subject to production test. 2. current is limited by bonding, with an r thjc = 2.1 c/w the chip is able to carry 32 a at 25 c. drain current (continuous) at t c = 25 c 20 a i d drain current (continuous) at t c = 100 c 20 a i d (4) drain current (continuous) at t pcb = 25 c 7.8 a i d (4) drain current (continuous) at t pcb =100 c 5.5 a i dm (3),(4) 3. pulse width limited by safe operating area. 4. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec drain current (pulsed) 31.2 a p tot total dissipation at t c = 25c 70 w p tot (4) total dissipation at t pcb = 25c 4.3 w i av not-repetitive avalanche current 7.8 a e as (5) 5. starting t j = 25 c, i d = 7.8 a, v dd = 25 v. single pulse avalanche energy 190 mj t j t stg operating junction temperature storage temperature -55 to 175 c table 3. thermal resistance symbol parameter value unit r thj-case thermal resistance junction-case 2.1 c/w r thj-pcb (1) 1. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10 sec thermal resistance junction-pcb 35 c/w
electrical characteristics STL8N10LF3 4/13 doc id 023977 rev 1 2 electrical characteristics (t case = 25 c unless otherwise specified) table 4. on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 250 a 100 v i dss zero gate voltage drain current (v gs = 0) v ds = 100 v 1 a i gss gate body leakage current (v ds = 0) v gs = 20 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 3 v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 4 a v gs = 5 v, i d = 4 a 25 40 35 50 m m table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25 v, f=1 mhz, v gs =0 - 970 115 11.5 - pf pf pf q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =50 v, i d = 7.8 a v gs =10 v figure 13 - 20.5 4 5 - nc nc nc r g intrinsic gate resistance f=1 mhz open drain 3.65 table 6. switching times symbol parameter test conditions min. typ. max. unit t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd =50 v, i d = 7.8 a, r g =4.7 , v gs =10 v figure 12 - 8.7 9.6 50.6 5.2 - ns ns ns ns
STL8N10LF3 electrical characteristics doc id 023977 rev 1 5/13 table 7. source drain diode symbol parameter test conditions min typ. max unit i sd source-drain current - 7.8 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) - 31.2 a v sd (2) 2. pulsed: pulse duration= 300 s, duty cycle 1.5% forward on voltage i sd = 7.8 a, v gs =0 - 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 7.8 a, di/dt = 100 a/s, v dd =48 v, tj=150 c - 42.5 87 4.08 ns nc a
electrical characteristics STL8N10LF3 6/13 doc id 023977 rev 1 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. normalized v ds vs temperature figure 7. static drain-source on-resistance i d 10 1 0.1 0.1 1 v d s (v) 10 (a) oper a tion in thi s a re a i s limited b y m a x r d s (on) 10m s 100m s 1 s tj=175c tc=25c s ingle p u l s e am1 3 017v1 10 -4 10 - 3 10 -2 10 -1 t p ( s ) 10 -2 10 -1 k 0.2 0.05 0.02 0.01 0.1 s ingle p u l s e =0.5 10 0 10 1 10 - 3 zth_am1 3 007v1 i d 15 10 5 0 0 2 v d s (v) 4 (a) 1 3 20 25 5v 4v v g s =10v am1 3 01 8 v1 i d 15 10 5 0 0 2 v g s (v) 4 (a) 1 3 20 25 v d s =4v am1 3 019v1 v d s -75 t j (c) (norm) -25 75 25 125 0.90 0.94 0.9 8 1.02 1.06 i d =1ma 1.10 am1 3 010v1 r d s (on) 25.0 24. 8 24.6 24.4 2 4 i d (a) (m ) 3 5 25.2 25.4 6 7 v g s =10v am1 3 020v1
STL8N10LF3 electrical characteristics doc id 023977 rev 1 7/13 figure 8. gate charge vs gate-source voltage figure 9. capacitance variations figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on-resistance vs temperature v g s 6 4 2 0 0 5 q g (nc) (v) 20 8 10 15 10 v dd =50v i d =7. 8 a am1 3 021v1 c 1000 100 10 0 40 v d s (v) (pf) 20 60 ci ss co ss cr ss 8 0 am1 3 022v1 v g s (th) 1.0 0. 8 0.6 0.4 -75 t j (c) (norm) -25 1.2 75 25 125 i d =250 a am1 3 014v1 r d s (on) 1.2 0. 8 0.4 0 -75 t j (c) (norm) -25 75 25 125 1.6 2.0 i d =4a v g s =10v am1 3 015v1
test circuits STL8N10LF3 8/13 doc id 023977 rev 1 3 test circuits figure 12. switching times test circuit for resistive load figure 13. gate charge test circuit figure 14. test circuit for inductive load switching and diode recovery times figure 15. unclamped inductive load test circuit figure 16. unclamped inductive waveform figure 17. switching time waveform am0146 8 v1 v g s p w v d r g r l d.u.t. 2200 f 3 . 3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =con s t 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fa s t diode d s l=100 h f 3 . 3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3 . 3 f v dd am01472v1 v (br)d ss v dd v dd v d i dm i d am0147 3 v1 v d s t on td on td off t off t f t r 90 % 10 % 10 % 0 0 90 % 90 % 10 % v g s
STL8N10LF3 package mechanical data doc id 023977 rev 1 9/13 4 package mechanical data table 8. powerflat 5x6 type s-r mechanical data dim. mm min. typ. max. a0.80 1.00 a1 0.02 0.05 a2 0.25 b0.30 0.50 d5.005.205.40 e5.956.156.35 d2 4.11 4.31 e2 3.50 3.70 e1.27 l0.60 0.80 k 1.275 1.575
package mechanical data STL8N10LF3 10/13 doc id 023977 rev 1 figure 18. powerflat 5x6 type s-r drawing 8 2 3 1 8 17_rev.f_ri bb on type s -r bottom view s ide view to p v i e w
STL8N10LF3 package mechanical data doc id 023977 rev 1 11/13 figure 19. powerflat 5x6 recommended footprint (dimensions are in mm) footprint
revision history STL8N10LF3 12/13 doc id 023977 rev 1 5 revision history table 9. document revision history date revision changes 17-jan-2013 1 first release.
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